1. Field of the Invention
The present invention relates generally to memory cell structures employed within semiconductor integrated circuit fabrications. More particularly, the present invention relates to methods for forming memory cell structures employed within semiconductor integrated circuit fabrications.
2. Description of the Related Art
Semiconductor integrated circuit fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices, and over which are formed patterned conductor layers which are separated by dielectric layers.
Common in the art of semiconductor integrated circuit fabrication, and in particular in the art of semiconductor integrated circuit memory fabrication, is the use and the fabrication of memory cell structures, and in particular dynamic random access memory (DRAM) cell structures. Dynamic random access memory (DRAM) cell structures typically comprises a field effect transistor (FET) device formed within and upon a semiconductor substrate, where one of a pair of source/drain regions within the field effect transistor (FET) device has formed thereover and electrically connected therewith a storage capacitor. Within a dynamic random access memory (DRAM) cell structure, a gate electrode of the field effect transistor (FET) device serves as a wordline which provides a switching function for charge introduction into and retrieval from the storage capacitor, while the other of the pair of source/drain regions within the field effect transistor (FET) device serves as a contact for a bitline conductor stud which introduces or retrieves charge with respect to the storage capacitor.
While the dynamic random access memory (DRAM) cell structure has clearly become ubiquitous in the art of semiconductor integrated circuit memory fabrication, and is thus essential in the art of semiconductor integrated circuit fabrication, the dynamic random access memory (DRAM) cell structure is nonetheless not entirely without problems in the art of semiconductor integrated circuit memory fabrication.
In that regard, as semiconductor integration levels have increased and semiconductor device and patterned conductor layer dimensions have decreased, it has become increasingly common in the art of semiconductor integrated circuit fabrication, and in particular in the art of semiconductor integrated circuit memory fabrication, to readily form dynamic random access memory (DRAM) cell structures with enhanced performance.
It is thus desirable in the art of semiconductor integrated circuit fabrication, and in particular in the art of semiconductor integrated circuit memory fabrication, to provide methods and materials through which there may be readily formed, with enhanced performance, dynamic random access memory (DRAM) cell structures.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor integrated circuit fabrication for forming, with desirable properties, dynamic random access memory (DRAM) cell structures.
Included among the methods, but not limited among the methods, are methods disclosed within: (1) Lee, in U.S. Pat. No. 6,074,918 (a method for forming a capacitor and bitline structure within a dynamic random access memory (DRAM) cell structure for use within a semiconductor integrated circuit memory fabrication, with improved alignment and etching margin, by forming a bitline contact stud layer independently of, and of a different height than, a capacitor contact stud layer); (2) Chi, in U.S. Pat. No. 6,174,767 (a method for forming a capacitor and bitline structure within a dynamic random access memory (DRAM) cell structure for use within a semiconductor integrated circuit memory fabrication, with attenuated bitline to bitline capacitance within the capacitor and bitline structure, by forming a pair of bitline structures within the capacitor and bitline structure at an equivalent topographic level with a capacitor within the capacitor and bitline structure); and (3) Chen, in U.S. Pat. No. 6,207,579 (a method for forming a capacitor and bitline structure within a dynamic random access memory (DRAM) cell structure for use within a semiconductor integrated circuit memory fabrication, with enhanced alignment, by forming a bitline conductor layer in a self-aligned fashion with respect to a pair of capacitor contact stud layers).
Desirable in the art of semiconductor integrated circuit fabrication, and in particular in the art of semiconductor integrated circuit memory fabrication, are additional methods and materials which may be employed for readily forming, with enhanced performance, dynamic random access memory (DRAM) cell structures.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a method for forming a dynamic random access memory (DRAM) cell structure within a semiconductor integrated circuit fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the dynamic random access memory (DRAM) cell structure is readily formed with enhanced performance.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a pair of methods for forming a memory cell structure.
To practice a first of the methods of the present invention, there is provided a semiconductor substrate. There is then formed within and upon the semiconductor substrate a field effect transistor (FET) device comprising a gate dielectric layer formed upon the semiconductor substrate, a gate electrode formed upon the gate dielectric layer and a pair of source/drain regions formed into the semiconductor substrate and separated by the gate electrode. There is then formed over the field effect transistor (FET) device, and electrically connected with one of the pair of source/drain regions, a capacitor structure having a sidewall. There is then formed laterally adjacent the sidewall of the capacitor structure a sacrificial spacer layer. There is then formed laterally adjacent the sacrificial spacer layer and further spaced from the sidewall of the capacitor structure a passivating dielectric layer. There is then formed through the passivating dielectric layer a bitline stud layer electrically connected with the other of the pair of source/drain regions. Finally, there is also stripped from adjacent the sidewall of the capacitor structure the sacrificial spacer, such as to provide an air gap void interposed between the capacitor structure and bitline stud layer.
To practice a second of the methods of the present invention, there is also first provided a semiconductor substrate. There is also then formed within and upon the semiconductor substrate a field effect transistor (FET) device comprising a gate dielectric layer formed upon the semiconductor substrate, a gate electrode formed upon the gate dielectric layer and a pair of source/drain regions formed into the semiconductor substrate and separated by the gate electrode. There is then formed over the field effect transistor (FET) device, and electrically connected with one of the pair of source/drain regions, a capacitor structure comprising a blanket capacitor plate layer having an upper topographic portion and a lower topographic portion. There is then formed over the blanket capacitor plate layer a variable thickness blanket mask layer having a greater thickness over the upper topographic portion of the blanket capacitor plate layer than over the lower topographic portion of the blanket capacitor plate layer. Finally, there is then etched completely through the lower topographic portion of the variable thickness blanket mask layer and blanket capacitor plate layer to form a patterned capacitor plate layer having formed thereupon a variable thickness patterned mask layer.
The present invention provides a pair of methods for forming a dynamic random access memory (DRAM) cell structure within a semiconductor integrated circuit fabrication, wherein the dynamic random access memory (DRAM) cell structure is readily formed with enhanced performance.
A first of the methods of the present invention realizes the foregoing object by employing when forming a memory cell structure for use within a semiconductor integrated circuit fabrication an air gap void interposed, at least in part, between: (1) a sidewall of a capacitor structure electrically connected with one of a pair of source/drain regions within a field effect transistor (FET) device within the memory cell structure; and (2) a bitline stud layer electrically connected with the other of the pair of source/drain regions within the field effect transistor (FET) device, where the bitline stud layer is adjacent to and extends above the sidewall of the capacitor structure. Within the first of the methods of the present invention, the air gap void provides for attenuated capacitor structure to bitline stud layer parasitic capacitance. In addition, within the first of the methods of the present invention, the air gap void is formed through selective removal of an anisotropically etched spacer layer formed adjacent a sidewall of the capacitor structure.
A second of the methods of the present invention realizes the foregoing object by employing for forming within a memory cell structure a patterned capacitor plate layer from a blanket capacitor plate layer having an upper topographic portion and a lower topographic portion a variable thickness blanket mask layer formed over the blanket capacitor plate layer. The variable thickness blanket mask layer has a greater thickness over the upper topographic portion of the blanket capacitor plate layer and a lesser thickness over the lower topographic portion of the blanket capacitor plate layer. By employing the variable thickness blanket mask layer formed over the blanket capacitor plate layer, the patterned capacitor plate layer may be formed from the blanket capacitor plate layer in a self aligned fashion by completely etching through the lower topographic portion of both the variable thickness blanket mask layer and the blanket capacitor plate layer but not completely through the upper topographic portion of either the variable thickness blanket mask layer or the blanket capacitor plate layer.
The methods of the present invention are readily commercially implemented.
The present invention employs methods and materials as are generally known in the art of semiconductor integrated circuit fabrication, but employed within the context of specific process orderings and specific materials limitations to provide a pair of methods for forming a pair of memory cell structures in accord with the present invention. Since it is thus at least in part specific process orderings and specific materials limitations which provide at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the methods of the present invention are readily commercially implemented.